doc.# dsfp-TC7920 b080613 TC7920 features ? high voltage vertical dmos technology ? integrated drain output high voltage diodes ? integrated gate-to-source resistor ? integrated gate-to-source zener diode ? low threshold, low on-resistance ? low input & output capacitance ? fast switching speeds ? electrically isolated n- and p-mosfet pairs applications ? high voltage pulsers ? amplifers ? buffers ? piezoelectric transducer drivers ? general purpose line drivers ? logic level interfaces two pair, n- and p-channel enhancement-mode mosfet with drain-diodes general description the superte x TC7920 consists of two pairs of high voltage, low threshold n-channel and p-channel mosfets in a 12-lead dfn package. all mosfets have integrated the output drain high voltage diodes, gate-to-source resistors and gate-to-source zener diode clamps which are desired for high voltage pulser applications. the complimentary, high-speed, high voltage, gate- clamped n and p-channel mosfet pairs utilize an advanced vertical dmos structure and supertexs well-proven silicon-gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coeffcient inherent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input and output capacitance, and fast switching speeds are desired. typical application circuit 1.8 to 5.0v logic imput s outb vdd vh ina inb oe 0.1f +10v supertex tc7 9 2 0 damp vl gnd inc ind vss +pulse -pulse enab v pp +100v 10nf supertex md1822 0.47f outa outd outc 1.0f 1.0f v nn -100v supertex inc. supertex inc. www .supertex.com
2 doc.# dsfp-TC7920 b080613 TC7920 absolute maximum ratings parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs operating and storage temperature -55c to +150c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. 12-lead dfn package marking package may or may not include the following marks: si or note: 1.0oz, 4-layer, 3x4 pcb. 7920 ywll y = last digit of year sealed w = code for week sealed l = lot number = ?green? packaging pin confguration 12-lead dfn (top view) 1 2 3 4 5 6 12 11 10 9 8 7 sn1 dn1 dp1 sp1 dn2 dp2 gn1 gp1 gn2 sn2 gp2 sp2 thermal pad typical thermal resistance package ja 12-lead dfn 42 o c/w ordering information part number package option packing TC7920k6-g 12-lead dfn 3000/reel product summary bv dss /bv dgs r ds(on) (max) n-channel p-channel n-channel p-channel 200v -200v 7.0 8.0 sym parameter min typ max unit condition v r breakdown voltage 200 - - v i r = 100a vf forward voltage - 1.25 - v i f = 100ma i fm park forward current - 3.0 - a 3xovhzlgwk v 2hglrgh i r reverse current - 1.0 - a v r = 100 v, t a = 25 o c - 100 - v r = 100 v, t a = 125 o c t rr reverse recovery time - 1.0 - s i f = i r = 10ma, i rr = 1.0 ma, r l drain output diodes pin description pin # function description pin # function description 1 gn1 gate of n-mosfet 1 7 dp2 drain of p-mosfet 2 2 gp1 gate of p-mosfet 1 8 dn2 drain of n-mosfet 2 3 gn2 gate of n-mosfet 2 9 sp1 source of p-mosfet 1 4 sn2 source of n-mosfet 2 10 dp1 drain of p-mosfet 1 5 gp2 gate of p-mosfet 2 11 dn1 drain of n-mosfet 1 6 sp2 source of p-mosfet 2 12 sn1 source of n-mosfet 1 thermal pad die attachment substrate, must be grounded externally supertex inc. www .supertex.com
3 doc.# dsfp-TC7920 b080613 TC7920 n-channel switching waveforms and test circuit 10 % 90 % 90 % 10 % 90 % 10 % r gen in put puls e ge ne ra to r v dd r l d. u. t output t r t f t d(on) t (on) t d(off) t (off) 10v input 0v vdd output 0v n-channel electrical characteristics (t a = 25c unless otherwise specifed) sym parameter min typ max units conditions bv dss drain-to-source breakdown voltage 200 - - v v gs = 0v, i d = 2.0ma v gs(th) gate threshold voltage 1.0 - 2.4 v v gs = v ds , i d = 1.0ma v gs(th) change in v gs(th) with temperature - - -4.5 mv/ o c v gs = v ds , i d = 1.0ma r gs gate-to-source shunt resistor 10 - 50 k i gs = 100a vz gs gate-to-source zener voltage 13.2 - 25 v i gs = 2.0ma i dss zero gate voltage drain current - - 10.0 a v ds = max rating, v gs = 0v - - 1.0 ma v ds = 0.8 max rating, v gs = 0v, t a = 125 o c i d(on) on-state drain current 0.9 - - a v gs = 5.0v, v ds = 25v 2.0 - - v gs = 10v, v ds = 50v r ds(on) static drain-to-source on-state resistance - - 13 v gs = 5.0v, i d = 150ma - - 10 v gs = 10v, i d = 1.0a r ds(on) change in r ds(on) with temperature - - 1.0 %/ o c v gs = 5.0v, i d =150ma g fs forward transconductance 300 - - mmho v ds = 25v, i d = 500ma c iss input capacitance - 52 - pf v gs = 0v, v ds = 25v, f = 1.0mhz c oss common source output capacitance - 6.9 - c rss reverse transfer capacitance - 1.3 - t d(on) turn-on delay time - - 10 ns v dd =25v, i d = 1.0a, r gen = 25? t r rise time - - 15 t d(off) turn-off delay time - - 20 t f fall time - - 15 v sd diode forward voltage drop - - 1.8 v v gs = 0v, i sd = 500ma t rr reverse recovery time - 300 - ns v gs = 0v, i sd = 500ma notes: 1. all d.c. parameters 100% tested at 25 o c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. supertex inc. www .supertex.com
4 doc.# dsfp-TC7920 b080613 TC7920 p-channel electrical characteristics (t a = 25c unless otherwise specifed) sym parameter min typ max units conditions bv dss drain-to-source breakdown voltage -200 - - v v gs = 0v, i d = -2.0ma v gs(th) gate threshold voltage -1.0 - -2.4 v v gs = v ds , i d = -1.0ma v gs(th) change in v gs(th) with temperature - - 4.5 mv/ o c v gs = v ds , i d = -1.0ma r gs gate-to-source shunt resistor 10 - 50 k i gs = 100a vz gs gate-to-source zener voltage 13.2 - 25 v i gs = -2.0ma i dss zero gate voltage drain current - - -10 a v ds = max rating, v gs = 0v - - -1.0 ma v ds = 0.8 max rating, v gs = 0v, t a = 125 o c i d(on) on-state drain current -0.7 - - a v gs = -5.0v, v ds = -25v -2.0 - - v gs = -10v, v ds = -50v r ds(on) static drain-to-source on-state resistance - - 15 v gs = -5.0v, i d = -150ma - - 12 v gs = -10v, i d = -1.0a r ds(on) change in r ds(on) with temperature - - 1.0 %/ o c v gs = -10v, i d =-200ma g fs forward transconductance 300 - - mmho v ds = -25v, i d = -500ma c iss input capacitance - 54 - pf v gs = 0v, v ds = -25v, f = 1.0mhz c oss common source output capacitance - 7.5 - c rss reverse transfer capacitance - 2.6 - t d(on) turn-on delay time - - 10 ns v dd = -25v, i d = -1.0a, r gen = 25 t r rise time - - 15 t d(off) turn-off delay time - - 20 t f fall time - - 15 v sd diode forward voltage drop - - -1.8 v v gs = 0v, i sd = -500ma t rr reverse recovery time - 300 - ns v gs = 0v, i sd = -500ma notes: 1. all d.c. parameters 100% tested at 25 o c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. p-channel switching waveforms and test circuit r gen in pu t pul se ge ne ra to r v dd r l d. u. t output 0v input -10v t r t f t d(on) t (on) 90 % 10 % 90 % 10 % 10 % 90 % t d(off) t (off) 0v output vdd supertex inc. www .supertex.com
5 TC7920 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-TC7920 b080613 12-lead dfn package outline (k6) 4.00x4.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 3.85 3.19 3.85 2.29 0.50 bsc 0.30 0.00 0 o nom 0.90 0.02 0.25 4.00 3.34 4.00 2.44 0.40 - - max 1.00 0.05 0.30 4.15 3.44 4.15 2.54 0.50 0.15 14 o drawings not to scale. supertex doc.#: dspd-12dfnk64x4p050, version a030210. seating plane t op vi ew side v iew bottom v iew a a1 d e d2 e b e2 a3 l l1 v iew b vi ew b note 1 (index area d/2 x e/2) note 3 note 2 note 1 (index area d/2 x e/2) 12 1 12 1 notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
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